Ebook: Computer Engineering and Technology: 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers

This book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others.

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This book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012.
The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others.

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This book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012.
The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others.
Content:
Front Matter....Pages -
A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU....Pages 1-7
Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method....Pages 8-15
MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processor....Pages 16-26
An Efficient Parallel SURF Algorithm for Multi-core Processor....Pages 27-37
A Study of Cache Design in Stream Processor....Pages 38-48
Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor....Pages 49-56
Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecture....Pages 57-66
ADL and High Performance Processor Design....Pages 67-74
The Design of the ROHC Header Compression Accelerator....Pages 75-83
A Hardware Implementation of Nussinov RNA Folding Algorithm....Pages 84-91
A Configurable Architecture for 1-D Discrete Wavelet Transform....Pages 92-101
A Comparison of Folded Architectures for the Discrete Wavelet Transform....Pages 102-110
A High Performance DSP System with Fault Tolerant for Space Missions....Pages 111-120
The Design and Realization of Campus Information Release Platform Based on Android Framework....Pages 121-128
A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method....Pages 129-137
DAMQ Sharing Scheme for Two Physical Channels in High Performance Router....Pages 138-147
Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip....Pages 148-154
HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip....Pages 155-162
Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator....Pages 163-172
A Quick Method for Mapping Cores Onto 2D-Mesh Based Networks on Chip....Pages 173-184
A Combined Hardware/Software Measurement for ARM Program Execution Time....Pages 185-201
A Low-Complexity Parallel Two-Sided Jacobi Complex SVD Algorithm and Architecture for MIMO Beamforming Systems....Pages 202-210
A Thermal-Aware Task Mapping Algorithm for Coarse Grain Reconfigurable Computing System....Pages 211-220
DC Offset Mismatch Calibration for Time-Interleaved ADCs in High-Speed OFDM Receivers....Pages 221-230
A Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures....Pages 231-241
Memristor Working Condition Analysis Based on SPICE Model....Pages 242-252
On Stepsize of Fast Subspace Tracking Methods....Pages 253-261
Back Matter....Pages -

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This book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012.
The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others.
Content:
Front Matter....Pages -
A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU....Pages 1-7
Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method....Pages 8-15
MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processor....Pages 16-26
An Efficient Parallel SURF Algorithm for Multi-core Processor....Pages 27-37
A Study of Cache Design in Stream Processor....Pages 38-48
Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor....Pages 49-56
Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecture....Pages 57-66
ADL and High Performance Processor Design....Pages 67-74
The Design of the ROHC Header Compression Accelerator....Pages 75-83
A Hardware Implementation of Nussinov RNA Folding Algorithm....Pages 84-91
A Configurable Architecture for 1-D Discrete Wavelet Transform....Pages 92-101
A Comparison of Folded Architectures for the Discrete Wavelet Transform....Pages 102-110
A High Performance DSP System with Fault Tolerant for Space Missions....Pages 111-120
The Design and Realization of Campus Information Release Platform Based on Android Framework....Pages 121-128
A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method....Pages 129-137
DAMQ Sharing Scheme for Two Physical Channels in High Performance Router....Pages 138-147
Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip....Pages 148-154
HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip....Pages 155-162
Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator....Pages 163-172
A Quick Method for Mapping Cores Onto 2D-Mesh Based Networks on Chip....Pages 173-184
A Combined Hardware/Software Measurement for ARM Program Execution Time....Pages 185-201
A Low-Complexity Parallel Two-Sided Jacobi Complex SVD Algorithm and Architecture for MIMO Beamforming Systems....Pages 202-210
A Thermal-Aware Task Mapping Algorithm for Coarse Grain Reconfigurable Computing System....Pages 211-220
DC Offset Mismatch Calibration for Time-Interleaved ADCs in High-Speed OFDM Receivers....Pages 221-230
A Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures....Pages 231-241
Memristor Working Condition Analysis Based on SPICE Model....Pages 242-252
On Stepsize of Fast Subspace Tracking Methods....Pages 253-261
Back Matter....Pages -
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