Ebook: Reconfigurable Computing: Architectures and Applications: Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers

1 The International Workshop on Recon?gurable Computing (ARC) started in 2005 in Algarve, Portugal. The major motivation was to create an event where on-going research e?orts as well as more elaborated, interesting and hi- quality work on applied recon?gurable computing could be presented and d- cussed. Over the last couple of years recon?gurable computing has become a we- known and established research area producing interesting as well as important results in both general and embedded computing systems. It is also getting more and more interest from industry which is attracted by the (design and development) ?exibility as well as the performance improvements that can be expected from this technology. As recon?gurablecomputing has blurred the gap between software and hardware, some even speak of a radical new programming paradigm opening a new realm of unseen applications and opportunities. The logo of the ARC workshop is the Nonius, a measurement instrument used in the Portuguese period of discoveries that was invented by Pedro Nunes, a Portuguesemathematician. As the logo suggests,the main motto of ARC is to help to navigate the world of recon?gurable computing. Driven by this motto, we hope ARC contributes to solid advances on recon?gurable computing.

---

This book constitutes the thoroughly refereed post-proceedings of the Second International Workshop on Reconfigurable Computing, ARC 2006, held in Delft, The Netherlands, in March 2006.

The 22 revised full papers and 35 revised short papers presented were thoroughly reviewed and selected from 95 submissions. The papers are organized in topical sections on applications, power, image processing, organization and architecture, networks and communication, security, and tools.

---

This book constitutes the thoroughly refereed post-proceedings of the Second International Workshop on Reconfigurable Computing, ARC 2006, held in Delft, The Netherlands, in March 2006.

The 22 revised full papers and 35 revised short papers presented were thoroughly reviewed and selected from 95 submissions. The papers are organized in topical sections on applications, power, image processing, organization and architecture, networks and communication, security, and tools.

Content:
Front Matter....Pages -
Implementation of Realtime and Highspeed Phase Detector on FPGA....Pages 1-11
Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform....Pages 12-17
Configurable Embedded Core for Controlling Electro-Mechanical Systems....Pages 18-23
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors....Pages 24-29
Dynamic Partial Reconfigurable FIR Filter Design....Pages 30-35
Event-Driven Simulation Engine for Spiking Neural Networks on a Chip....Pages 36-45
Towards an Optimal Implementation of MLP in FPGA....Pages 46-51
Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture....Pages 52-58
Quality Driven Dynamic Low Power Reconfiguration of Handhelds....Pages 59-64
An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects....Pages 65-74
Highly Paralellized Architecture for Image Motion Estimation....Pages 75-86
Design Exploration of a Video Pre-processor for an FPGA Based SoC....Pages 87-92
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection....Pages 93-98
Applications of Small-Scale Reconfigurability to Graphics Processors....Pages 99-108
An Embedded Multi-camera System for Simultaneous Localization and Mapping....Pages 109-114
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor....Pages 115-121
Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip....Pages 122-127
Handel-C Design Enhancement for FPGA-Based DV Decoder....Pages 128-133
Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform....Pages 134-145
A New VLSI Architecture of Lifting-Based DWT....Pages 146-151
Architecture Based on FPGA’s for Real-Time Image Processing....Pages 152-157
Real Time Image Processing on a Portable Aid Device for Low Vision Patients....Pages 158-163
General Purpose Real-Time Image Segmentation System....Pages 164-169
Implementation of LPM Address Generators on FPGAs....Pages 170-181
Self Reconfiguring EPIC Soft Core Processors....Pages 182-186
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs....Pages 187-192
Area/Performance Improvement of NoC Architectures....Pages 193-198
Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array....Pages 199-204
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms....Pages 205-216
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support....Pages 217-229
A Reconfigurable Data Cache for Adaptive Processors....Pages 230-242
The Emergence of Non-von Neumann Processors....Pages 243-254
Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server....Pages 255-261
A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs....Pages 262-267
A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI....Pages 268-273
PISC: Polymorphic Instruction Set Computers....Pages 274-286
Generic Network Interfaces for Plug and Play NoC Based Architecture....Pages 287-298
Providing QoS Guarantees in a NoC by Virtual Channel Reservation....Pages 299-310
Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA....Pages 311-316
A Reconfigurable Architecture for MIMO Square Root Decoder....Pages 317-322
Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking....Pages 323-334
Updates on the Security of FPGAs Against Power Analysis Attacks....Pages 335-346
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems....Pages 347-357
Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider....Pages 358-369
UNITE: Uniform Hardware-Based Network Intrusion deTection Engine....Pages 370-382
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs....Pages 383-388
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection....Pages 389-400
A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware....Pages 401-412
Hardware and a Tool Chain for ADRES....Pages 413-418
Integrating Custom Instruction Specifications into C Development Processes....Pages 419-424
A Compiler-Oriented Architecture Description for Reconfigurable Systems....Pages 425-430
Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility....Pages 431-442
High-Level Synthesis Using SPARK and Systolic Array....Pages 443-448
Super Semi-systolic Array-Based Application-Specific PLD Architecture....Pages 449-454
Back Matter....Pages 455-460
....Pages 461-466