Ebook: Defect and Fault Tolerance in VLSI Systems: Volume 1

This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition­ ers from both industry and academia in the field of defect tolerance and yield en­ ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.

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Content:
Front Matter....Pages i-xii
Yield Models for Defect-Tolerant VLSI Circuits: A Review....Pages 1-21
Wafer Scale Revisited....Pages 23-31
Defects, Faults and Semiconductor Device Yield....Pages 33-46
On the Probability of Fault Occurrence....Pages 47-52
A New Yield Formula for Fault-Tolerant Large-Area Devices....Pages 53-64
Defect Tolerant Interconnects for VLSI....Pages 65-76
Combining Architecture and Algorithm for Yield Enhancement and Fault Tolerance....Pages 77-84
Design of a Fault-Tolerant DRAM with New On-Chip ECC....Pages 85-92
Measurement and Distribution of Faults on Defect Test Site Chips....Pages 93-104
Process Development and Circuit Design Interactions in VLSI Yield Improvement....Pages 105-116
Yield Projection Based on Electrical Fault Distribution and Critical Structure Analysis....Pages 117-127
Yield Model for Yield Projection from Test Site....Pages 129-137
Test Methods for Wafer-Scale Integration....Pages 139-148
Fault Diagnosis of Linear Processor Arrays....Pages 149-160
Fault Diagnosis of Array Processors with Uniformly Distributed Faults....Pages 161-170
Designing for High Yield: The NS32532 Microprocessor....Pages 171-177
Defect Tolerance in a 16-Bit Microprocessor....Pages 179-190
Design Techniques for a Self-Checking Self-Exercising Processor....Pages 191-202
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors....Pages 203-212
Diagnosis and Repair of Large Memories: A Critical Review and Recent Results....Pages 213-225
A Reconfigurable SRAM 4.5 Mbit WSI Memory....Pages 227-242
Block Alignment: A Method for Increasing the Yield of Memory Chips That are Partially Good....Pages 243-255
Fault Tolerant Integrated Memory Design....Pages 257-267
Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays....Pages 269-280
Fabrication-Time and Run-Time Fault-Tolerant Array Processors Using Single-Track Switches....Pages 281-294
An Efficient Restructuring Approach for Wafer Scale Processor Arrays....Pages 295-307
Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-D Arrays....Pages 309-318
A General Model for Fault Covering Problems in Reconfigurable Arrays....Pages 319-326
Defect Tolerance in a Wafer Scale Array for Image Processing....Pages 327-338
Distributed Fault Tolerant Embedding of Binary Trees and Rings in Hypercubes....Pages 339-346
On the Analysis and Design of Hierarchical Fault-Tolerant Processor Arrays....Pages 347-355
Back Matter....Pages 357-362

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Content:
Front Matter....Pages i-xii
Yield Models for Defect-Tolerant VLSI Circuits: A Review....Pages 1-21
Wafer Scale Revisited....Pages 23-31
Defects, Faults and Semiconductor Device Yield....Pages 33-46
On the Probability of Fault Occurrence....Pages 47-52
A New Yield Formula for Fault-Tolerant Large-Area Devices....Pages 53-64
Defect Tolerant Interconnects for VLSI....Pages 65-76
Combining Architecture and Algorithm for Yield Enhancement and Fault Tolerance....Pages 77-84
Design of a Fault-Tolerant DRAM with New On-Chip ECC....Pages 85-92
Measurement and Distribution of Faults on Defect Test Site Chips....Pages 93-104
Process Development and Circuit Design Interactions in VLSI Yield Improvement....Pages 105-116
Yield Projection Based on Electrical Fault Distribution and Critical Structure Analysis....Pages 117-127
Yield Model for Yield Projection from Test Site....Pages 129-137
Test Methods for Wafer-Scale Integration....Pages 139-148
Fault Diagnosis of Linear Processor Arrays....Pages 149-160
Fault Diagnosis of Array Processors with Uniformly Distributed Faults....Pages 161-170
Designing for High Yield: The NS32532 Microprocessor....Pages 171-177
Defect Tolerance in a 16-Bit Microprocessor....Pages 179-190
Design Techniques for a Self-Checking Self-Exercising Processor....Pages 191-202
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors....Pages 203-212
Diagnosis and Repair of Large Memories: A Critical Review and Recent Results....Pages 213-225
A Reconfigurable SRAM 4.5 Mbit WSI Memory....Pages 227-242
Block Alignment: A Method for Increasing the Yield of Memory Chips That are Partially Good....Pages 243-255
Fault Tolerant Integrated Memory Design....Pages 257-267
Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays....Pages 269-280
Fabrication-Time and Run-Time Fault-Tolerant Array Processors Using Single-Track Switches....Pages 281-294
An Efficient Restructuring Approach for Wafer Scale Processor Arrays....Pages 295-307
Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-D Arrays....Pages 309-318
A General Model for Fault Covering Problems in Reconfigurable Arrays....Pages 319-326
Defect Tolerance in a Wafer Scale Array for Image Processing....Pages 327-338
Distributed Fault Tolerant Embedding of Binary Trees and Rings in Hypercubes....Pages 339-346
On the Analysis and Design of Hierarchical Fault-Tolerant Processor Arrays....Pages 347-355
Back Matter....Pages 357-362
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