Ebook: Optimal VLSI Architectural Synthesis: Area, Performance and Testability
- Tags: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD CAE) and Design
- Series: The Kluwer International Series in Engineering and Computer Science 158
- Year: 1992
- Publisher: Springer US
- Edition: 1
- Language: English
- pdf
Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.
Content:
Front Matter....Pages i-xiv
Front Matter....Pages 1-1
Global VLSI Design Cycle....Pages 3-20
Behavioral and Structural Interfaces....Pages 21-36
Front Matter....Pages 37-37
State of the Art Synthesis....Pages 39-61
Introduction to Integer Programming....Pages 63-80
Front Matter....Pages 81-81
A Methodology for Architectural Synthesis....Pages 83-95
Simultaneous Scheduling, and Selection and Allocation of Functional Units....Pages 97-108
Oasic: Area-Delay Constrained Architectural Synthesis....Pages 109-122
Support for Algorithmic Constructs....Pages 123-128
Interface Constraints....Pages 129-140
Oasic Synthesis Results....Pages 141-175
Front Matter....Pages 177-177
Testability In Architectural Synthesis....Pages 179-205
The Catree Architectural Synthesis with Testability....Pages 207-258
Front Matter....Pages 259-259
Summary and Future Research....Pages 261-270
Back Matter....Pages 271-289
Content:
Front Matter....Pages i-xiv
Front Matter....Pages 1-1
Global VLSI Design Cycle....Pages 3-20
Behavioral and Structural Interfaces....Pages 21-36
Front Matter....Pages 37-37
State of the Art Synthesis....Pages 39-61
Introduction to Integer Programming....Pages 63-80
Front Matter....Pages 81-81
A Methodology for Architectural Synthesis....Pages 83-95
Simultaneous Scheduling, and Selection and Allocation of Functional Units....Pages 97-108
Oasic: Area-Delay Constrained Architectural Synthesis....Pages 109-122
Support for Algorithmic Constructs....Pages 123-128
Interface Constraints....Pages 129-140
Oasic Synthesis Results....Pages 141-175
Front Matter....Pages 177-177
Testability In Architectural Synthesis....Pages 179-205
The Catree Architectural Synthesis with Testability....Pages 207-258
Front Matter....Pages 259-259
Summary and Future Research....Pages 261-270
Back Matter....Pages 271-289
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