Ebook: VHDL for Simulation, Synthesis and Formal Proofs of Hardware

The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.

---

---

Content:
Front Matter....Pages i-ix
Evolutionary Processes in Language, Software, and System Design....Pages 1-13
Front Matter....Pages 15-15
Timing Constraint Checks in VHDL—a comparative study....Pages 17-32
Using Formalized Timing Diagrams in VHDL Simulation....Pages 33-42
Switch-Level Models in Multi-level VHDL Simulations....Pages 43-62
Bi-directional Switches in VHDL using the 46 Value System....Pages 63-71
Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL....Pages 73-86
Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design....Pages 87-98
Front Matter....Pages 99-99
A VHDL-Driven Synthesis Environment....Pages 101-115
VHDL Specific Issues in High Level Synthesis....Pages 117-133
ASIC Design Using Silicon 1076....Pages 135-147
Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool....Pages 149-161
Aspects of Optimization and Accuracy for VHDL Synthesis....Pages 163-175
Front Matter....Pages 177-177
Symbolic Computation of Hierarchical and Interconnected FSMS....Pages 179-193
Formal semantics of VHDL timing constructs....Pages 195-206
A Structural Information Model of VHDL....Pages 207-225
Formal verification of VHDL descriptions in Boyer-Moore : first results....Pages 227-243
Developing a Formal Semantic Definition of VHDL....Pages 245-256
Front Matter....Pages 257-257
Approaching System Level Design....Pages 259-276
Incremental Design—Application of a Software-based Method for High-level Hardware Design with VHDL....Pages 277-290
Introducing CASCADE control graphs in VHDL....Pages 291-307

---

Content:
Front Matter....Pages i-ix
Evolutionary Processes in Language, Software, and System Design....Pages 1-13
Front Matter....Pages 15-15
Timing Constraint Checks in VHDL—a comparative study....Pages 17-32
Using Formalized Timing Diagrams in VHDL Simulation....Pages 33-42
Switch-Level Models in Multi-level VHDL Simulations....Pages 43-62
Bi-directional Switches in VHDL using the 46 Value System....Pages 63-71
Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL....Pages 73-86
Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design....Pages 87-98
Front Matter....Pages 99-99
A VHDL-Driven Synthesis Environment....Pages 101-115
VHDL Specific Issues in High Level Synthesis....Pages 117-133
ASIC Design Using Silicon 1076....Pages 135-147
Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool....Pages 149-161
Aspects of Optimization and Accuracy for VHDL Synthesis....Pages 163-175
Front Matter....Pages 177-177
Symbolic Computation of Hierarchical and Interconnected FSMS....Pages 179-193
Formal semantics of VHDL timing constructs....Pages 195-206
A Structural Information Model of VHDL....Pages 207-225
Formal verification of VHDL descriptions in Boyer-Moore : first results....Pages 227-243
Developing a Formal Semantic Definition of VHDL....Pages 245-256
Front Matter....Pages 257-257
Approaching System Level Design....Pages 259-276
Incremental Design—Application of a Software-based Method for High-level Hardware Design with VHDL....Pages 277-290
Introducing CASCADE control graphs in VHDL....Pages 291-307
....