Ebook: Reconfigurable Computing: Architectures, Tools and Applications: 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings

This book constitutes the refereed proceedings of the 7th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2011, held in Belfast, UK, in March 2011. The 40 revised papers presented, consisting of 24 full papers, 14 poster papers, and the abstracts of 2 plenary talks, were carefully reviewed and selected from 88 submissions. The topics covered are reconfigurable accelerators, design tools, reconfigurable processors, applications, device architecture, methodology and simulation, and system architecture.

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This book constitutes the refereed proceedings of the 7th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2011, held in Belfast, UK, in March 2011. The 40 revised papers presented, consisting of 24 full papers, 14 poster papers, and the abstracts of 2 plenary talks, were carefully reviewed and selected from 88 submissions. The topics covered are reconfigurable accelerators, design tools, reconfigurable processors, applications, device architecture, methodology and simulation, and system architecture.

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This book constitutes the refereed proceedings of the 7th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2011, held in Belfast, UK, in March 2011. The 40 revised papers presented, consisting of 24 full papers, 14 poster papers, and the abstracts of 2 plenary talks, were carefully reviewed and selected from 88 submissions. The topics covered are reconfigurable accelerators, design tools, reconfigurable processors, applications, device architecture, methodology and simulation, and system architecture.
Content:
Front Matter....Pages -
Reconfigurable Computing for High Performance Networking Applications....Pages 1-1
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform....Pages 2-2
A Reconfigurable Audio Beamforming Multi-Core Processor....Pages 3-15
A Regular Expression Matching Circuit Based on a Decomposed Automaton....Pages 16-28
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios....Pages 29-40
Application Specific Memory Access, Reuse and Reordering for SDRAM....Pages 41-52
Automatic Generation of FPGA-Specific Pipelined Accelerators....Pages 53-66
HLS Tools for FPGA: Faster Development with Better Performance....Pages 67-78
A (Fault-Tolerant)2 Scheduler for Real-Time HW Tasks....Pages 79-87
A Compact Gaussian Random Number Generator for Small Word Lengths....Pages 88-93
Accurate Floating Point Arithmetic through Hardware Error-Free Transformations....Pages 94-101
Active Storage Networks for Accelerating K-Means Data Clustering....Pages 102-109
An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems....Pages 110-117
CReAMS: An Embedded Multiprocessor Platform....Pages 118-124
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture....Pages 125-132
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection....Pages 133-144
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL....Pages 145-156
Towards an Adaptable Multiple-ISA Reconfigurable Processor....Pages 157-168
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments....Pages 169-180
FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design....Pages 181-192
Index to Constant Weight Codeword Converter....Pages 193-205
On-Chip Ego-Motion Estimation Based on Optical Flow....Pages 206-217
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA....Pages 218-229
Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction....Pages 230-241
MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays....Pages 242-252
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA....Pages 253-260
Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications....Pages 261-268
Hierarchical Optical Flow Estimation Architecture Using Color Cues....Pages 269-274
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power....Pages 275-280
Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers....Pages 281-286
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA....Pages 287-295
A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology....Pages 296-301
FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations....Pages 302-315
FPGA Optimizations for a Pipelined Floating-Point Exponential Unit....Pages 316-327
NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security....Pages 328-339
A Correlation Power Analysis Attack against Tate Pairing on FPGA....Pages 340-349
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype....Pages 350-362
Architectural Support for Multithreading on Reconfigurable Hardware....Pages 363-374
High Performance Programmable FPGA Overlay for Digital Signal Processing....Pages 375-384
Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture....Pages 385-396
Back Matter....Pages -

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This book constitutes the refereed proceedings of the 7th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2011, held in Belfast, UK, in March 2011. The 40 revised papers presented, consisting of 24 full papers, 14 poster papers, and the abstracts of 2 plenary talks, were carefully reviewed and selected from 88 submissions. The topics covered are reconfigurable accelerators, design tools, reconfigurable processors, applications, device architecture, methodology and simulation, and system architecture.
Content:
Front Matter....Pages -
Reconfigurable Computing for High Performance Networking Applications....Pages 1-1
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform....Pages 2-2
A Reconfigurable Audio Beamforming Multi-Core Processor....Pages 3-15
A Regular Expression Matching Circuit Based on a Decomposed Automaton....Pages 16-28
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios....Pages 29-40
Application Specific Memory Access, Reuse and Reordering for SDRAM....Pages 41-52
Automatic Generation of FPGA-Specific Pipelined Accelerators....Pages 53-66
HLS Tools for FPGA: Faster Development with Better Performance....Pages 67-78
A (Fault-Tolerant)2 Scheduler for Real-Time HW Tasks....Pages 79-87
A Compact Gaussian Random Number Generator for Small Word Lengths....Pages 88-93
Accurate Floating Point Arithmetic through Hardware Error-Free Transformations....Pages 94-101
Active Storage Networks for Accelerating K-Means Data Clustering....Pages 102-109
An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems....Pages 110-117
CReAMS: An Embedded Multiprocessor Platform....Pages 118-124
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture....Pages 125-132
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection....Pages 133-144
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL....Pages 145-156
Towards an Adaptable Multiple-ISA Reconfigurable Processor....Pages 157-168
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments....Pages 169-180
FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design....Pages 181-192
Index to Constant Weight Codeword Converter....Pages 193-205
On-Chip Ego-Motion Estimation Based on Optical Flow....Pages 206-217
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA....Pages 218-229
Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction....Pages 230-241
MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays....Pages 242-252
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA....Pages 253-260
Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications....Pages 261-268
Hierarchical Optical Flow Estimation Architecture Using Color Cues....Pages 269-274
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power....Pages 275-280
Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers....Pages 281-286
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA....Pages 287-295
A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology....Pages 296-301
FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations....Pages 302-315
FPGA Optimizations for a Pipelined Floating-Point Exponential Unit....Pages 316-327
NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security....Pages 328-339
A Correlation Power Analysis Attack against Tate Pairing on FPGA....Pages 340-349
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype....Pages 350-362
Architectural Support for Multithreading on Reconfigurable Hardware....Pages 363-374
High Performance Programmable FPGA Overlay for Digital Signal Processing....Pages 375-384
Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture....Pages 385-396
Back Matter....Pages -
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