Ebook: Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
- Tags: Circuits and Systems, Computer-Aided Engineering (CAD CAE) and Design
- Year: 2012
- Publisher: Springer-Verlag New York
- Edition: 1
- Language: English
- pdf
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process.
This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
- Integrates power estimation and reduction for high level synthesis, with low-power, high-level design;
- Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives;
- Covers techniques from RTL/gate-level to hardware software co-design.
Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process.
This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
- Integrates power estimation and reduction for high level synthesis, with low-power, high-level design;
- Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives;
- Covers techniques from RTL/gate-level to hardware software co-design.
Content:
Front Matter....Pages i-xxii
Introduction....Pages 1-12
Related Work....Pages 13-29
Background....Pages 31-43
Architectural Selection Using High Level Synthesis....Pages 45-57
Statistical Regression Based Power Models....Pages 59-70
Coprocessor Design Space Exploration Using High Level Synthesis....Pages 71-80
Regression-Based Dynamic Power Estimation for FPGAs....Pages 81-92
High Level Simulation Directed RTL Power Estimation....Pages 93-103
Applying Verification Collaterals for Accurate Power Estimation....Pages 105-118
Power Reduction Using High-Level Clock-Gating....Pages 119-129
Model-Checking to Exploit Sequential Clock-Gating....Pages 131-141
System Level Simulation Guided Approach for Clock-Gating....Pages 143-156
Conclusions....Pages 157-161
Back Matter....Pages 163-170
Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process.
This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
- Integrates power estimation and reduction for high level synthesis, with low-power, high-level design;
- Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives;
- Covers techniques from RTL/gate-level to hardware software co-design.
Content:
Front Matter....Pages i-xxii
Introduction....Pages 1-12
Related Work....Pages 13-29
Background....Pages 31-43
Architectural Selection Using High Level Synthesis....Pages 45-57
Statistical Regression Based Power Models....Pages 59-70
Coprocessor Design Space Exploration Using High Level Synthesis....Pages 71-80
Regression-Based Dynamic Power Estimation for FPGAs....Pages 81-92
High Level Simulation Directed RTL Power Estimation....Pages 93-103
Applying Verification Collaterals for Accurate Power Estimation....Pages 105-118
Power Reduction Using High-Level Clock-Gating....Pages 119-129
Model-Checking to Exploit Sequential Clock-Gating....Pages 131-141
System Level Simulation Guided Approach for Clock-Gating....Pages 143-156
Conclusions....Pages 157-161
Back Matter....Pages 163-170
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