Ebook: Application-Specific Mesh-based Heterogeneous FPGA Architectures

Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption.

This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.

• Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures;
• Describes state-of-the-art techniques for reducing area requirements in FPGA architectures;
• Enables reduction in power required and increase in performance.
  

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Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption.

This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.

• Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures;
• Describes state-of-the-art techniques for reducing area requirements in FPGA architectures;
• Enables reduction in power required and increase in performance.
  

---

Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption.

This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.

• Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures;
• Describes state-of-the-art techniques for reducing area requirements in FPGA architectures;
• Enables reduction in power required and increase in performance.
  

Content:
Front Matter....Pages i-xvii
Introduction....Pages 1-8
State of the art....Pages 9-30
Heterogeneous FPGA Exploration Environment....Pages 31-60
FPGA Layout Generation....Pages 61-75
ASIF: Application Specific Inflexible FPGA....Pages 77-101
ASIF using Heterogeneous Logic Blocks....Pages 103-117
ASIF Hardware Generation....Pages 119-137
Conclusion and Future Lines of Research....Pages 139-144
Back Matter....Pages 145-150

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Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption.

This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.

• Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures;
• Describes state-of-the-art techniques for reducing area requirements in FPGA architectures;
• Enables reduction in power required and increase in performance.
  

Content:
Front Matter....Pages i-xvii
Introduction....Pages 1-8
State of the art....Pages 9-30
Heterogeneous FPGA Exploration Environment....Pages 31-60
FPGA Layout Generation....Pages 61-75
ASIF: Application Specific Inflexible FPGA....Pages 77-101
ASIF using Heterogeneous Logic Blocks....Pages 103-117
ASIF Hardware Generation....Pages 119-137
Conclusion and Future Lines of Research....Pages 139-144
Back Matter....Pages 145-150
....