Ebook: Low Power Networks-on-Chip

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

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Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

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Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
Content:
Front Matter....Pages i-xix
Front Matter....Pages 1-1
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections....Pages 3-20
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks....Pages 21-43
Adaptive Voltage Control for Energy-Efficient NoC Links....Pages 45-69
Asynchronous Communications for NoCs....Pages 71-109
Front Matter....Pages 111-111
Application-Specific Routing Algorithms for Low Power Network on Chip Design....Pages 113-150
Adaptive Data Compression for Low-Power On-Chip Networks....Pages 151-174
Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study....Pages 175-195
Front Matter....Pages 197-197
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs....Pages 199-222
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study....Pages 223-254
RF-Interconnect for Future Network-On-Chip....Pages 255-280
Back Matter....Pages 281-287

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Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
Content:
Front Matter....Pages i-xix
Front Matter....Pages 1-1
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections....Pages 3-20
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks....Pages 21-43
Adaptive Voltage Control for Energy-Efficient NoC Links....Pages 45-69
Asynchronous Communications for NoCs....Pages 71-109
Front Matter....Pages 111-111
Application-Specific Routing Algorithms for Low Power Network on Chip Design....Pages 113-150
Adaptive Data Compression for Low-Power On-Chip Networks....Pages 151-174
Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study....Pages 175-195
Front Matter....Pages 197-197
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs....Pages 199-222
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study....Pages 223-254
RF-Interconnect for Future Network-On-Chip....Pages 255-280
Back Matter....Pages 281-287
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