Ebook: On and Off-Chip Crosstalk Avoidance in VLSI Design

On- and Off-Chip Crosstalk Avoidance in VLSI Design

Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri

Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design.

This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book:

• Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster;
• Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based;
• Provides techniques to design extremely efficient CODECs for crosstalk cancellation;
• Provides crosstalk cancellation approaches for multi-valued busses;
• Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.

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On- and Off-Chip Crosstalk Avoidance in VLSI Design

Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri

Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design.

This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book:

• Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster;
• Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based;
• Provides techniques to design extremely efficient CODECs for crosstalk cancellation;
• Provides crosstalk cancellation approaches for multi-valued busses;
• Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.

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On- and Off-Chip Crosstalk Avoidance in VLSI Design

Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri

Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design.

This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book:

• Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster;
• Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based;
• Provides techniques to design extremely efficient CODECs for crosstalk cancellation;
• Provides crosstalk cancellation approaches for multi-valued busses;
• Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.

Content:
Front Matter....Pages 1-24
Front Matter....Pages 20-20
Introduction of On-Chip Crosstalk Avoidance....Pages 3-11
Preliminaries to On-chip Crosstalk....Pages 13-26
Memoryless Crosstalk Avoidance Codes....Pages 27-45
CODEC Designs for Memoryless Crosstalk Avoidance Codes....Pages 47-72
Memory-based Crosstalk Avoidance Codes....Pages 73-86
Multi-valued Logic Crosstalk Avoidance Codes....Pages 87-99
Summary of On-Chip Crosstalk Avoidance....Pages 101-103
Front Matter....Pages 105-105
Introduction to Off-Chip Crosstalk....Pages 107-124
Package Construction and Electrical Modeling....Pages 125-136
Preliminaries and Terminology....Pages 137-144
Analytical Model for Off-Chip Bus Performance....Pages 145-160
Optimal Bus Sizing....Pages 161-166
Bus Expansion Encoder....Pages 167-187
Bus Stuttering Encoder....Pages 189-199
Impedance Compensation....Pages 201-218
Future Trends and Applications....Pages 219-226
Summary of Off-Chip Crosstalk Avoidance....Pages 227-229
Back Matter....Pages 231-240

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On- and Off-Chip Crosstalk Avoidance in VLSI Design

Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri

Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design.

This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book:

• Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster;
• Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based;
• Provides techniques to design extremely efficient CODECs for crosstalk cancellation;
• Provides crosstalk cancellation approaches for multi-valued busses;
• Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.

Content:
Front Matter....Pages 1-24
Front Matter....Pages 20-20
Introduction of On-Chip Crosstalk Avoidance....Pages 3-11
Preliminaries to On-chip Crosstalk....Pages 13-26
Memoryless Crosstalk Avoidance Codes....Pages 27-45
CODEC Designs for Memoryless Crosstalk Avoidance Codes....Pages 47-72
Memory-based Crosstalk Avoidance Codes....Pages 73-86
Multi-valued Logic Crosstalk Avoidance Codes....Pages 87-99
Summary of On-Chip Crosstalk Avoidance....Pages 101-103
Front Matter....Pages 105-105
Introduction to Off-Chip Crosstalk....Pages 107-124
Package Construction and Electrical Modeling....Pages 125-136
Preliminaries and Terminology....Pages 137-144
Analytical Model for Off-Chip Bus Performance....Pages 145-160
Optimal Bus Sizing....Pages 161-166
Bus Expansion Encoder....Pages 167-187
Bus Stuttering Encoder....Pages 189-199
Impedance Compensation....Pages 201-218
Future Trends and Applications....Pages 219-226
Summary of Off-Chip Crosstalk Avoidance....Pages 227-229
Back Matter....Pages 231-240
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