Ebook: Power-Aware Testing and Test Strategies for Low Power Devices

Power-Aware Testing and Test Strategies for Low-Power Devices

Edited by:

Patrick Girard, Research Director, CNRS / LIRMM, France

Nicola Nicolici, Associate Professor, McMaster University, Canada

Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan

Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and Electronic Design Automation (EDA) solutions for testing low-power devices.

1. The first comprehensive book on power-aware test for (low-power) circuits and systems
2. Shows readers how low-power devices can be tested safely without affecting yield and reliability
3. Includes necessary background information on design-for-test and low-power design
4. Covers in detail power-constrained test techniques, including power-aware automatic test pattern generation, design-for-test, built-in self-test and test compression
5. Presents state-of-the-art industrial practices and EDA solutions

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Power-Aware Testing and Test Strategies for Low-Power Devices

Edited by:

Patrick Girard, Research Director, CNRS / LIRMM, France

Nicola Nicolici, Associate Professor, McMaster University, Canada

Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan

Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and Electronic Design Automation (EDA) solutions for testing low-power devices.

1. The first comprehensive book on power-aware test for (low-power) circuits and systems
2. Shows readers how low-power devices can be tested safely without affecting yield and reliability
3. Includes necessary background information on design-for-test and low-power design
4. Covers in detail power-constrained test techniques, including power-aware automatic test pattern generation, design-for-test, built-in self-test and test compression
5. Presents state-of-the-art industrial practices and EDA solutions

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Power-Aware Testing and Test Strategies for Low-Power Devices

Edited by:

Patrick Girard, Research Director, CNRS / LIRMM, France

Nicola Nicolici, Associate Professor, McMaster University, Canada

Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan

Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and Electronic Design Automation (EDA) solutions for testing low-power devices.

1. The first comprehensive book on power-aware test for (low-power) circuits and systems
2. Shows readers how low-power devices can be tested safely without affecting yield and reliability
3. Includes necessary background information on design-for-test and low-power design
4. Covers in detail power-constrained test techniques, including power-aware automatic test pattern generation, design-for-test, built-in self-test and test compression
5. Presents state-of-the-art industrial practices and EDA solutions

Content:
Front Matter....Pages i-xxiii
Fundamentals of VLSI Testing....Pages 1-29
Power Issues During Test....Pages 31-63
Low-Power Test Pattern Generation....Pages 65-115
Power-Aware Design-for-Test....Pages 117-146
Power-Aware Test Data Compression and BIST....Pages 147-173
Power-Aware System-Level Test Planning....Pages 175-211
Low-Power Design Techniques and Test Implications....Pages 213-242
Test Strategies for Multivoltage Designs....Pages 243-271
Test Strategies for Gated Clock Designs....Pages 273-293
Test of Power Management Structures....Pages 295-322
EDA Solution for Power-Aware Design-for-Test....Pages 323-353
Back Matter....Pages 355-363

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Power-Aware Testing and Test Strategies for Low-Power Devices

Edited by:

Patrick Girard, Research Director, CNRS / LIRMM, France

Nicola Nicolici, Associate Professor, McMaster University, Canada

Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan

Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and Electronic Design Automation (EDA) solutions for testing low-power devices.

1. The first comprehensive book on power-aware test for (low-power) circuits and systems
2. Shows readers how low-power devices can be tested safely without affecting yield and reliability
3. Includes necessary background information on design-for-test and low-power design
4. Covers in detail power-constrained test techniques, including power-aware automatic test pattern generation, design-for-test, built-in self-test and test compression
5. Presents state-of-the-art industrial practices and EDA solutions

Content:
Front Matter....Pages i-xxiii
Fundamentals of VLSI Testing....Pages 1-29
Power Issues During Test....Pages 31-63
Low-Power Test Pattern Generation....Pages 65-115
Power-Aware Design-for-Test....Pages 117-146
Power-Aware Test Data Compression and BIST....Pages 147-173
Power-Aware System-Level Test Planning....Pages 175-211
Low-Power Design Techniques and Test Implications....Pages 213-242
Test Strategies for Multivoltage Designs....Pages 243-271
Test Strategies for Gated Clock Designs....Pages 273-293
Test of Power Management Structures....Pages 295-322
EDA Solution for Power-Aware Design-for-Test....Pages 323-353
Back Matter....Pages 355-363
....