Ebook: Nanometer Technology Designs High-Quality Delay Tests
- Tags: Circuits and Systems, Electronics and Microelectronics Instrumentation, Computer-Aided Engineering (CAD CAE) and Design, Nanotechnology, Electrical Engineering
- Year: 2008
- Publisher: Springer US
- Edition: 1
- Language: English
- pdf
While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip defects. For nanometer technology designs, the traditional test methods cannot ensure a high quality level of chips, and at-speed tests using path and transition delay fault model have become a requirement in technologies below 180nm.
Nanometer Technology Designs: High-Quality Delay Tests discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the delay test for nanotechnology designs. Topics covered include:
- At-speed test challenges for nanotechnology
- Low-cost tester-friendly design-for-test techniques
- Improving test quality of current at-speed test methods
- Functionally un-testable fault list generation and avoidance
- Timing-based ATPG for screening small delay faults
- Faster-than-at-speed test considering power supply noise
- Power supply noise tolerant at-speed test pattern generation and application
- Solutions for dealing with crosstalk and signal integrity issues
Nanometer Technology Designs: High-Quality Delay Tests is a reference for practicing engineers and researchers in both industry and academia who are interested in learning about and implementing the most-advanced methods in nanometer delay testing.
While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip defects. For nanometer technology designs, the traditional test methods cannot ensure a high quality level of chips, and at-speed tests using path and transition delay fault model have become a requirement in technologies below 180nm.
Nanometer Technology Designs: High-Quality Delay Tests discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the delay test for nanotechnology designs. Topics covered include:
- At-speed test challenges for nanotechnology
- Low-cost tester-friendly design-for-test techniques
- Improving test quality of current at-speed test methods
- Functionally un-testable fault list generation and avoidance
- Timing-based ATPG for screening small delay faults
- Faster-than-at-speed test considering power supply noise
- Power supply noise tolerant at-speed test pattern generation and application
- Solutions for dealing with crosstalk and signal integrity issues
Nanometer Technology Designs: High-Quality Delay Tests is a reference for practicing engineers and researchers in both industry and academia who are interested in learning about and implementing the most-advanced methods in nanometer delay testing.
While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip defects. For nanometer technology designs, the traditional test methods cannot ensure a high quality level of chips, and at-speed tests using path and transition delay fault model have become a requirement in technologies below 180nm.
Nanometer Technology Designs: High-Quality Delay Tests discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the delay test for nanotechnology designs. Topics covered include:
- At-speed test challenges for nanotechnology
- Low-cost tester-friendly design-for-test techniques
- Improving test quality of current at-speed test methods
- Functionally un-testable fault list generation and avoidance
- Timing-based ATPG for screening small delay faults
- Faster-than-at-speed test considering power supply noise
- Power supply noise tolerant at-speed test pattern generation and application
- Solutions for dealing with crosstalk and signal integrity issues
Nanometer Technology Designs: High-Quality Delay Tests is a reference for practicing engineers and researchers in both industry and academia who are interested in learning about and implementing the most-advanced methods in nanometer delay testing.
Content:
Front Matter....Pages I-XVII
Introduction....Pages 1-28
At-speed Test Challenges for Nanometer Technology Designs....Pages 29-43
Local At-Speed Scan Enable Generation Using Low-Cost Testers....Pages 45-72
Enhanced Launch-Off-Capture....Pages 73-99
Hybrid Scan-Based Transition Delay Test....Pages 101-120
Avoiding Functionally Untestable Faults....Pages 121-134
Screening Small Delay Defects....Pages 135-155
Faster-Than-At-Speed Test Considering IR-drop Effects....Pages 157-175
IR-drop Tolerant At-speed Test Pattern Generation....Pages 177-205
Pattern Generation for Power Supply Noise Analysis....Pages 207-221
Delay Fault Testing in Presence of Maximum Crosstalk....Pages 223-240
Testing SoC Interconnects for Signal Integrity....Pages 241-275
Back Matter....Pages 277-281
While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip defects. For nanometer technology designs, the traditional test methods cannot ensure a high quality level of chips, and at-speed tests using path and transition delay fault model have become a requirement in technologies below 180nm.
Nanometer Technology Designs: High-Quality Delay Tests discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the delay test for nanotechnology designs. Topics covered include:
- At-speed test challenges for nanotechnology
- Low-cost tester-friendly design-for-test techniques
- Improving test quality of current at-speed test methods
- Functionally un-testable fault list generation and avoidance
- Timing-based ATPG for screening small delay faults
- Faster-than-at-speed test considering power supply noise
- Power supply noise tolerant at-speed test pattern generation and application
- Solutions for dealing with crosstalk and signal integrity issues
Nanometer Technology Designs: High-Quality Delay Tests is a reference for practicing engineers and researchers in both industry and academia who are interested in learning about and implementing the most-advanced methods in nanometer delay testing.
Content:
Front Matter....Pages I-XVII
Introduction....Pages 1-28
At-speed Test Challenges for Nanometer Technology Designs....Pages 29-43
Local At-Speed Scan Enable Generation Using Low-Cost Testers....Pages 45-72
Enhanced Launch-Off-Capture....Pages 73-99
Hybrid Scan-Based Transition Delay Test....Pages 101-120
Avoiding Functionally Untestable Faults....Pages 121-134
Screening Small Delay Defects....Pages 135-155
Faster-Than-At-Speed Test Considering IR-drop Effects....Pages 157-175
IR-drop Tolerant At-speed Test Pattern Generation....Pages 177-205
Pattern Generation for Power Supply Noise Analysis....Pages 207-221
Delay Fault Testing in Presence of Maximum Crosstalk....Pages 223-240
Testing SoC Interconnects for Signal Integrity....Pages 241-275
Back Matter....Pages 277-281
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