Ebook: Leakage in Nanometer CMOS Technologies

Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers.

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The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction.

Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles.  The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions.

Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions.  Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

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The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction.

Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles.  The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions.

Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions.  Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

Content:
Front Matter....Pages i-x
Taxonomy of Leakage: Sources, Impact, and Solutions....Pages 1-19
Leakage Dependence on Input Vector....Pages 21-39
Power Gating and Dynamic Voltage Scaling....Pages 41-75
Methodologies for Power Gating....Pages 77-104
Body Biasing....Pages 105-140
Process Variation and Adaptive Design....Pages 141-162
Memory Leakage Reduction....Pages 163-199
Active Leakage Reduction and Multi-Performance Devices....Pages 201-209
Impact of Leakage Power and Variation on Testing....Pages 211-233
Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors....Pages 235-255
Case Study: Leakage Reduction in the Intel Xscale Microprocessor....Pages 257-280
Transistor Design to Reduce Leakage....Pages 281-299
Back Matter....Pages 301-307

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The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction.

Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles.  The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions.

Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions.  Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

Content:
Front Matter....Pages i-x
Taxonomy of Leakage: Sources, Impact, and Solutions....Pages 1-19
Leakage Dependence on Input Vector....Pages 21-39
Power Gating and Dynamic Voltage Scaling....Pages 41-75
Methodologies for Power Gating....Pages 77-104
Body Biasing....Pages 105-140
Process Variation and Adaptive Design....Pages 141-162
Memory Leakage Reduction....Pages 163-199
Active Leakage Reduction and Multi-Performance Devices....Pages 201-209
Impact of Leakage Power and Variation on Testing....Pages 211-233
Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors....Pages 235-255
Case Study: Leakage Reduction in the Intel Xscale Microprocessor....Pages 257-280
Transistor Design to Reduce Leakage....Pages 281-299
Back Matter....Pages 301-307
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