Ebook: Interconnect Noise Optimization in Nanometer Technologies
- Tags: Circuits and Systems, Computer-Aided Engineering (CAD CAE) and Design, Computer Hardware, Electronic and Computer Engineering
- Year: 2006
- Publisher: Springer US
- Edition: 1
- Language: English
- pdf
Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.
The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.
The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.
The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Content:
Front Matter....Pages i-xix
Introduction....Pages 1-3
Noise Analysis and Design in Deep Submicron....Pages 5-28
Interconnect Noise Analysis and Optimization Techniques....Pages 29-43
Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies....Pages 45-57
Minimum Area Shield Insertion for Inductive Noise Reduction....Pages 59-73
Spacing Algorithms for Crosstalk Noise Reduction....Pages 75-78
Post Layout Interconnect Optimization for Crosscoupling Noise Reduction....Pages 79-93
3D Integration....Pages 95-105
EDA Industry Tools: State of the ART....Pages 107-123
Back Matter....Pages 125-137
Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.
The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Content:
Front Matter....Pages i-xix
Introduction....Pages 1-3
Noise Analysis and Design in Deep Submicron....Pages 5-28
Interconnect Noise Analysis and Optimization Techniques....Pages 29-43
Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies....Pages 45-57
Minimum Area Shield Insertion for Inductive Noise Reduction....Pages 59-73
Spacing Algorithms for Crosstalk Noise Reduction....Pages 75-78
Post Layout Interconnect Optimization for Crosscoupling Noise Reduction....Pages 79-93
3D Integration....Pages 95-105
EDA Industry Tools: State of the ART....Pages 107-123
Back Matter....Pages 125-137
....