Ebook: Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog

Principles of Verifiable RTL Design: A Functional Coding StyleSupporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
The intended audience for Principles of Verifiable RTL Design: AFunctional Coding Style Supporting Verification Processes inVerilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset.
Principles of Verifiable RTL Design: A Functional Coding StyleSupporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.

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Principles of Verifiable RTL Design: A Functional Coding StyleSupporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
The intended audience for Principles of Verifiable RTL Design: AFunctional Coding Style Supporting Verification Processes inVerilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset.
Principles of Verifiable RTL Design: A Functional Coding StyleSupporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.
Content:
Front Matter....Pages i-xvii
Introduction....Pages 1-8
The Verification Process....Pages 9-35
RTL Methodology Basics....Pages 37-62
RTL Logic Simulation....Pages 63-94
RTL Formal Verification....Pages 95-122
Verifiable RTL Style....Pages 123-160
The Bad Stuff....Pages 161-192
Verifiable RTL Tutorial....Pages 193-222
Principles of Verifiable RTL Design....Pages 223-230
Back Matter....Pages 231-253

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Principles of Verifiable RTL Design: A Functional Coding StyleSupporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
The intended audience for Principles of Verifiable RTL Design: AFunctional Coding Style Supporting Verification Processes inVerilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset.
Principles of Verifiable RTL Design: A Functional Coding StyleSupporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.
Content:
Front Matter....Pages i-xvii
Introduction....Pages 1-8
The Verification Process....Pages 9-35
RTL Methodology Basics....Pages 37-62
RTL Logic Simulation....Pages 63-94
RTL Formal Verification....Pages 95-122
Verifiable RTL Style....Pages 123-160
The Bad Stuff....Pages 161-192
Verifiable RTL Tutorial....Pages 193-222
Principles of Verifiable RTL Design....Pages 223-230
Back Matter....Pages 231-253
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