Ebook: Verilog — 2001: A Guide to the New Features of the Verilog® Hardware Description Language

by Phil Moorby The Verilog Hardware Description Language has had an amazing impact on the mod­ em electronics industry, considering that the essential composition of the language was developed in a surprisingly short period of time, early in 1984. Since its introduc­ tion, Verilog has changed very little. Over time, users have requested many improve­ ments to meet new methodology needs. But, it is a complex and time consuming process to add features to a language without ambiguity, and maintaining consistency. A group of Verilog enthusiasts, the IEEE 1364 Verilog committee, have broken the Verilog feature doldrums. These individuals should be applauded. They invested the time and energy, often their personal time, to understand and resolve an extensive wish-list of language enhancements. They took on the task of choosing a feature set that would stand up to the scrutiny of the standardization process. I would like to per­ sonally thank this group. They have shown that it is possible to evolve Verilog, rather than having to completely start over with some revolutionary new language. The Verilog 1364-2001 standard provides many of the advanced building blocks that users have requested. The enhancements include key components for verification, abstract design, and other new methodology capabilities. As designers tackle advanced issues such as automated verification, system partitioning, etc., the Verilog standard will rise to meet the continuing challenge of electronics design.

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Content:
Front Matter....Pages i-xi
Introduction....Pages 3-5
What’s new in Verilog-2001....Pages 7-7
Combined port and data type declarations....Pages 8-9
ANSI C style module declarations....Pages 10-11
Module port parameter lists....Pages 12-13
ANSI C style UDP declarations....Pages 14-15
Variable initial value at declaration....Pages 16-17
ANSI C style task/function declarations....Pages 18-19
Automatic (re-entrant) tasks....Pages 20-21
Automatic (recursive) functions....Pages 22-23
Constant functions....Pages 24-25
Comma separated sensitivity lists....Pages 26-27
Combinational logic sensitivity lists....Pages 28-31
Implicit nets for continuous assignments....Pages 32-33
Disabling implicit net declarations....Pages 34-35
Variable vector part selects....Pages 36-37
Multidimensional arrays....Pages 38-39
Arrays of net and real data types....Pages 40-40
Array bit and part selects....Pages 41-41
Signed reg, net and port declarations....Pages 42-43
Signed based integer numbers....Pages 44-45
Signed functions....Pages 46-47
Sign conversion system functions....Pages 48-49
Arithmetic shift operators....Pages 50-51
Assignment width extension past 32 bits....Pages 52-53
Power operator....Pages 54-55
Attributes....Pages 56-58
Sized and typed parameter constants....Pages 59-61
Explicit in-line parameter redefinition....Pages 62-63
Fixed local parameters....Pages 64-65
Standard random number generator....Pages 66-66
Extended number of open files....Pages 67-69
Enhanced file I/O....Pages 70-75
String read and write system tasks....Pages 76-77
Enhanced invocation option testing....Pages 78-79
Enhanced conditional compilation....Pages 80-81
Source file and line compiler directive....Pages 82-83
Generate blocks....Pages 84-89
Configurations....Pages 90-93
On-detect pulse error propagation....Pages 94-95
Negative pulse detection....Pages 96-97
Enhanced input timing checks....Pages 98-99
Negative input timing constraints....Pages 100-101
Enhanced SDF file support....Pages 102-103
Extended VCD files....Pages 104-105
Enhanced PLA system tasks....Pages 106-106
Enhanced Verilog PLI support....Pages 107-108
Back Matter....Pages 109-135

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Content:
Front Matter....Pages i-xi
Introduction....Pages 3-5
What’s new in Verilog-2001....Pages 7-7
Combined port and data type declarations....Pages 8-9
ANSI C style module declarations....Pages 10-11
Module port parameter lists....Pages 12-13
ANSI C style UDP declarations....Pages 14-15
Variable initial value at declaration....Pages 16-17
ANSI C style task/function declarations....Pages 18-19
Automatic (re-entrant) tasks....Pages 20-21
Automatic (recursive) functions....Pages 22-23
Constant functions....Pages 24-25
Comma separated sensitivity lists....Pages 26-27
Combinational logic sensitivity lists....Pages 28-31
Implicit nets for continuous assignments....Pages 32-33
Disabling implicit net declarations....Pages 34-35
Variable vector part selects....Pages 36-37
Multidimensional arrays....Pages 38-39
Arrays of net and real data types....Pages 40-40
Array bit and part selects....Pages 41-41
Signed reg, net and port declarations....Pages 42-43
Signed based integer numbers....Pages 44-45
Signed functions....Pages 46-47
Sign conversion system functions....Pages 48-49
Arithmetic shift operators....Pages 50-51
Assignment width extension past 32 bits....Pages 52-53
Power operator....Pages 54-55
Attributes....Pages 56-58
Sized and typed parameter constants....Pages 59-61
Explicit in-line parameter redefinition....Pages 62-63
Fixed local parameters....Pages 64-65
Standard random number generator....Pages 66-66
Extended number of open files....Pages 67-69
Enhanced file I/O....Pages 70-75
String read and write system tasks....Pages 76-77
Enhanced invocation option testing....Pages 78-79
Enhanced conditional compilation....Pages 80-81
Source file and line compiler directive....Pages 82-83
Generate blocks....Pages 84-89
Configurations....Pages 90-93
On-detect pulse error propagation....Pages 94-95
Negative pulse detection....Pages 96-97
Enhanced input timing checks....Pages 98-99
Negative input timing constraints....Pages 100-101
Enhanced SDF file support....Pages 102-103
Extended VCD files....Pages 104-105
Enhanced PLA system tasks....Pages 106-106
Enhanced Verilog PLI support....Pages 107-108
Back Matter....Pages 109-135
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