Ebook: Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

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Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

---

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
Content:
Front Matter....Pages i-xxxii
Introduction....Pages 5-45
A Quick Tour of Logic Synthesis with the Help of a Simple Example....Pages 47-76
Boolean Algebras....Pages 77-126
Synthesis of Two-Level Circuits....Pages 127-183
Heuristic Minimization of Two-level Circuits....Pages 185-218
Binary Decision Diagrams (BDDs)....Pages 219-254
Models of Sequential Systems....Pages 255-324
Synthesis and Verification of Finite State Machines....Pages 325-368
Finite Automata....Pages 369-403
Multi-Level Logic Synthesis....Pages 409-453
Multi-Level Minimization....Pages 455-474
Automatic Test Generation for Combinational Circuits....Pages 475-503
Technology Mapping....Pages 505-521
Back Matter....Pages 523-564

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Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
Content:
Front Matter....Pages i-xxxii
Introduction....Pages 5-45
A Quick Tour of Logic Synthesis with the Help of a Simple Example....Pages 47-76
Boolean Algebras....Pages 77-126
Synthesis of Two-Level Circuits....Pages 127-183
Heuristic Minimization of Two-level Circuits....Pages 185-218
Binary Decision Diagrams (BDDs)....Pages 219-254
Models of Sequential Systems....Pages 255-324
Synthesis and Verification of Finite State Machines....Pages 325-368
Finite Automata....Pages 369-403
Multi-Level Logic Synthesis....Pages 409-453
Multi-Level Minimization....Pages 455-474
Automatic Test Generation for Combinational Circuits....Pages 475-503
Technology Mapping....Pages 505-521
Back Matter....Pages 523-564
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