Ebook: The Verillog® Hardware Description Language

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

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Content:
Front Matter....Pages i-xxi
Verilog — A Tutorial Introduction....Pages 1-34
Logic Synthesis....Pages 35-71
Behavioral Modeling....Pages 73-107
Concurrent Processes....Pages 109-142
Module Hierarchy....Pages 143-155
Logic Level Modeling....Pages 157-193
Cycle-Accurate Specification....Pages 195-210
Advanced Timing....Pages 211-238
User-Defined Primitives....Pages 239-250
Switch Level Modeling....Pages 251-282
Projects....Pages 283-292
Back Matter....Pages 293-381

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Content:
Front Matter....Pages i-xxi
Verilog — A Tutorial Introduction....Pages 1-34
Logic Synthesis....Pages 35-71
Behavioral Modeling....Pages 73-107
Concurrent Processes....Pages 109-142
Module Hierarchy....Pages 143-155
Logic Level Modeling....Pages 157-193
Cycle-Accurate Specification....Pages 195-210
Advanced Timing....Pages 211-238
User-Defined Primitives....Pages 239-250
Switch Level Modeling....Pages 251-282
Projects....Pages 283-292
Back Matter....Pages 293-381
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