Ebook: System-on-Chip Methodologies & Design Languages

System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

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System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

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System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.
Content:
Front Matter....Pages i-x
Front Matter....Pages 1-1
VHDL in 2005 — The Requirements....Pages 3-12
Application of VHDL Features for Optimisation of Functional Validation Quality Measurement....Pages 13-24
An Object-Oriented Component Model Using Standard VHDL for Mixed Abstraction Level Design....Pages 25-36
A VHDL-Centric Mixed-Language Simulation Environment....Pages 37-46
Analogue circuit synthesis from VHDL-AMS....Pages 47-56
Front Matter....Pages 57-57
Symbolic Simulation and Verification of VHDL with ACL2....Pages 59-69
Functional Verification with Embedded Checkers....Pages 71-80
Improved Design Verification by Random Simulation Guided by Genetic Algorithms....Pages 81-95
VERIS: An Efficient Model Checker for Synchronous VHDL Designs....Pages 97-107
Front Matter....Pages 109-109
Title On Flip-flop Inference in HDL Synthesis....Pages 111-122
Synthesis Oriented Communication Design for Structural Hardware Objects....Pages 123-134
High-Level Synthesis through Transforming VHDL Models....Pages 135-146
Front Matter....Pages 147-147
Multi-Facetted Modeling....Pages 149-159
A Dual Spring System Case-Study Model in Rosetta....Pages 161-170
Transformational System Design Based on Formal Computational Model and Skeletons....Pages 171-185
Models of asynchronous computation....Pages 187-192
A mixed event-value based specification model for reactive systems....Pages 193-204
Jester....Pages 205-214
A four-phase handshaking asynchronous controller specification style and its idle-phase optimization....Pages 215-229
Front Matter....Pages 231-231
Automating the Validation of Hardware Description Language Processing Tools....Pages 233-244
Front Matter....Pages 231-231
A Retargetable Software Power Estimation Methodology....Pages 245-254
Performance Tradeoffs for Emulation, Hardware Acceleration, and Simulation....Pages 255-267
TCL_PLI, a Framework for Reusable, Run Time Configurable Test Benches....Pages 269-281
Front Matter....Pages 283-283
Object-Oriented Specification and Design of Embedded Hard Real-Time Systems....Pages 285-296
System Level Design for SOC’s....Pages 297-306
Virtual Component Reuse and Qualification for Digital and Analogue Design....Pages 307-316
Interface Based Design....Pages 317-331
Virtual Component HW/SW Co-Design....Pages 333-342

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System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.
Content:
Front Matter....Pages i-x
Front Matter....Pages 1-1
VHDL in 2005 — The Requirements....Pages 3-12
Application of VHDL Features for Optimisation of Functional Validation Quality Measurement....Pages 13-24
An Object-Oriented Component Model Using Standard VHDL for Mixed Abstraction Level Design....Pages 25-36
A VHDL-Centric Mixed-Language Simulation Environment....Pages 37-46
Analogue circuit synthesis from VHDL-AMS....Pages 47-56
Front Matter....Pages 57-57
Symbolic Simulation and Verification of VHDL with ACL2....Pages 59-69
Functional Verification with Embedded Checkers....Pages 71-80
Improved Design Verification by Random Simulation Guided by Genetic Algorithms....Pages 81-95
VERIS: An Efficient Model Checker for Synchronous VHDL Designs....Pages 97-107
Front Matter....Pages 109-109
Title On Flip-flop Inference in HDL Synthesis....Pages 111-122
Synthesis Oriented Communication Design for Structural Hardware Objects....Pages 123-134
High-Level Synthesis through Transforming VHDL Models....Pages 135-146
Front Matter....Pages 147-147
Multi-Facetted Modeling....Pages 149-159
A Dual Spring System Case-Study Model in Rosetta....Pages 161-170
Transformational System Design Based on Formal Computational Model and Skeletons....Pages 171-185
Models of asynchronous computation....Pages 187-192
A mixed event-value based specification model for reactive systems....Pages 193-204
Jester....Pages 205-214
A four-phase handshaking asynchronous controller specification style and its idle-phase optimization....Pages 215-229
Front Matter....Pages 231-231
Automating the Validation of Hardware Description Language Processing Tools....Pages 233-244
Front Matter....Pages 231-231
A Retargetable Software Power Estimation Methodology....Pages 245-254
Performance Tradeoffs for Emulation, Hardware Acceleration, and Simulation....Pages 255-267
TCL_PLI, a Framework for Reusable, Run Time Configurable Test Benches....Pages 269-281
Front Matter....Pages 283-283
Object-Oriented Specification and Design of Embedded Hard Real-Time Systems....Pages 285-296
System Level Design for SOC’s....Pages 297-306
Virtual Component Reuse and Qualification for Digital and Analogue Design....Pages 307-316
Interface Based Design....Pages 317-331
Virtual Component HW/SW Co-Design....Pages 333-342
....