Ebook: Reuse Methodology Manual: For System-on-a-Chip Designs

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available.
These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity.
Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual forSystem-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.

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Content:
Front Matter....Pages i-xxiii
Introduction....Pages 1-10
The System-on-a-Chip Design Process....Pages 11-24
System-Level Design Issues: Rules and Tools....Pages 25-52
The Macro Design Process....Pages 53-72
RTL Coding Guidelines....Pages 73-125
Macro Synthesis Guidelines....Pages 127-143
Macro Verification Guidelines....Pages 145-170
Developing Hard Macros....Pages 171-197
Macro Deployment: Packaging for Reuse....Pages 199-206
System Integration with Reusable Macros....Pages 207-228
System-Level Verification Issues....Pages 229-251
Data and Project Management....Pages 253-259
Implementing a Reuse Process....Pages 261-276
Back Matter....Pages 277-286

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Content:
Front Matter....Pages i-xxiii
Introduction....Pages 1-10
The System-on-a-Chip Design Process....Pages 11-24
System-Level Design Issues: Rules and Tools....Pages 25-52
The Macro Design Process....Pages 53-72
RTL Coding Guidelines....Pages 73-125
Macro Synthesis Guidelines....Pages 127-143
Macro Verification Guidelines....Pages 145-170
Developing Hard Macros....Pages 171-197
Macro Deployment: Packaging for Reuse....Pages 199-206
System Integration with Reusable Macros....Pages 207-228
System-Level Verification Issues....Pages 229-251
Data and Project Management....Pages 253-259
Implementing a Reuse Process....Pages 261-276
Back Matter....Pages 277-286
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