Ebook: Logic Synthesis for Low Power VLSI Designs

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

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Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

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Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
Content:
Front Matter....Pages i-xv
Front Matter....Pages 1-1
Introduction....Pages 3-19
Technology Independent Power Analysis and Modeling....Pages 21-39
Front Matter....Pages 41-41
Two-Level Logic Minimization in CMOS Circuits....Pages 43-67
Two-Level Logic Minimization in PLAs....Pages 69-84
Front Matter....Pages 85-85
Logic Restructuring for Low Power....Pages 87-107
Logic Minimization for Low Power....Pages 109-148
Technology Dependent Optimization for Low Power....Pages 149-182
Post Mapping Structural Optimization for Low Power....Pages 183-195
Front Matter....Pages 197-197
POSE: Power Optimization and Synthesis Environment....Pages 199-224
Front Matter....Pages 225-225
Concluding Remarks....Pages 227-232
Back Matter....Pages 233-236

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Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
Content:
Front Matter....Pages i-xv
Front Matter....Pages 1-1
Introduction....Pages 3-19
Technology Independent Power Analysis and Modeling....Pages 21-39
Front Matter....Pages 41-41
Two-Level Logic Minimization in CMOS Circuits....Pages 43-67
Two-Level Logic Minimization in PLAs....Pages 69-84
Front Matter....Pages 85-85
Logic Restructuring for Low Power....Pages 87-107
Logic Minimization for Low Power....Pages 109-148
Technology Dependent Optimization for Low Power....Pages 149-182
Post Mapping Structural Optimization for Low Power....Pages 183-195
Front Matter....Pages 197-197
POSE: Power Optimization and Synthesis Environment....Pages 199-224
Front Matter....Pages 225-225
Concluding Remarks....Pages 227-232
Back Matter....Pages 233-236
....