Ebook: Formal Equivalence Checking and Design Debugging

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley

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Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley

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Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley
Content:
Front Matter....Pages i-xviii
Introduction....Pages 1-14
Front Matter....Pages 15-15
Symbolic Verification....Pages 17-37
Incremental Verification for Combinational Circuits....Pages 39-60
Incremental Verification for Sequential Circuits....Pages 61-90
AQUILA: A Local BDD-based Equivalence Verifier....Pages 91-109
Algorithm for Verifying Retimed Circuits....Pages 111-121
RTL-to-Gate Verification....Pages 123-136
Front Matter....Pages 137-137
Introduction to Logic Debugging....Pages 139-157
ErrorTracer: Error Diagnosis by Fault Simulation....Pages 159-174
Extension to Sequential Error Diagnosis....Pages 175-187
Incremental Logic Rectification....Pages 189-209
Back Matter....Pages 211-229

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Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley
Content:
Front Matter....Pages i-xviii
Introduction....Pages 1-14
Front Matter....Pages 15-15
Symbolic Verification....Pages 17-37
Incremental Verification for Combinational Circuits....Pages 39-60
Incremental Verification for Sequential Circuits....Pages 61-90
AQUILA: A Local BDD-based Equivalence Verifier....Pages 91-109
Algorithm for Verifying Retimed Circuits....Pages 111-121
RTL-to-Gate Verification....Pages 123-136
Front Matter....Pages 137-137
Introduction to Logic Debugging....Pages 139-157
ErrorTracer: Error Diagnosis by Fault Simulation....Pages 159-174
Extension to Sequential Error Diagnosis....Pages 175-187
Incremental Logic Rectification....Pages 189-209
Back Matter....Pages 211-229
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