Ebook: Practical Formal Methods for Hardware Design

Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.

---

Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.

---

Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.
Content:
Front Matter....Pages I-XIV
Introduction....Pages 1-4
Front Matter....Pages 5-5
Design Methodology for Complex VLSI Devices....Pages 7-22
Specification Languages....Pages 23-51
Verification Flow....Pages 52-80
Synthesis Flow....Pages 81-96
Front Matter....Pages 97-97
Application of a Formal Verification Toolset to the Design of Integrated Circuits in an Industrial Environment....Pages 99-131
Italtel Application of the FORMAT Design Flow....Pages 132-158
Siemens Industrial Experience....Pages 159-172
Front Matter....Pages 173-173
The FORMAT Model Checker....Pages 175-183
Reasoning....Pages 184-216
VHDL Formal Modeling and Analysis....Pages 217-228
Synthesis Techniques....Pages 229-265
Generating VHDL Code from LOTOS Descriptions....Pages 266-293

---

Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.
Content:
Front Matter....Pages I-XIV
Introduction....Pages 1-4
Front Matter....Pages 5-5
Design Methodology for Complex VLSI Devices....Pages 7-22
Specification Languages....Pages 23-51
Verification Flow....Pages 52-80
Synthesis Flow....Pages 81-96
Front Matter....Pages 97-97
Application of a Formal Verification Toolset to the Design of Integrated Circuits in an Industrial Environment....Pages 99-131
Italtel Application of the FORMAT Design Flow....Pages 132-158
Siemens Industrial Experience....Pages 159-172
Front Matter....Pages 173-173
The FORMAT Model Checker....Pages 175-183
Reasoning....Pages 184-216
VHDL Formal Modeling and Analysis....Pages 217-228
Synthesis Techniques....Pages 229-265
Generating VHDL Code from LOTOS Descriptions....Pages 266-293
....