Ebook: Coupled Data Communication Techniques for High-Performance and Low-Power Computing

Designers of next-generation high-performance computer systems face a host of technical challenges. For the past several decades, rising clock frequencies and increased chip integration have fueled the growth of computer performance. Now these trends have slowed: power and complexity constrains further increases in clock frequencies, and economic realities limit the pace of Moore's Law. Coupled data communication provides a way forward, and this book, Coupled Data Communication Techniques for High-Performance and Low-Power Computing, gives a comprehensive overview for such coupled data techniques. Coupled data communication allows chips to communicate—capacitively or inductively—over short distances between chips without solder, and fundamentally shifts the design paradigm from single-chip integration to single-package integration. This book covers the state-of-the-art in the circuits, architectures, and chip packaging for this novel chip-to-chip communication technology and showcases its potential to drive the coming decades of industry growth. Coupled Data Communication Techniques for High-Performance and Low-Power Computing should be of interest to students and designers in circuits and system architecture.

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This book provides an overview of the circuits, architectures, and chip packaging for coupled data techniques. It discusses the current research in chip-to-board capacitive coupling, chip-to-chip capacitive coupling, chip-to-chip inductive coupling, and chip-to-chip optical coupling. Circuits, modeling, and their implications for packaging are explored in depth. Mechanical methods to ensure accurate and sustained chip alignment are discussed, as well as electrical methods to compensate for resulting misalignment. Finally, the book covers issues raised by design for manufacturing and test. This book is one of the first in a new and emerging area. Coupled data communication offers new ways of looking at the old problem of limited off-chip I/O: it trades off packaging complexity for I/O performance; it offers a set of enabling technologies for 3D or stacked-chip architectures; and it raises the possibility of replace-able chips--and thus high yield--in an MCM.