Ebook: Analog integrated circuit design

"The 2nd Edition of Analog Integrated Circuit Design focuses on more coverage about several types of circuits that have increased in importance in the past decade. Furthermore, the text is enhanced with material on CMOS IC device modeling, updated processing layout and expanded coverage to reflect technical innovations. CMOS devices and circuits have more influence in this edition as well as a reduced amount of text on BiCMOS and bipolar information. New chapters include topics on frequency response of analog ICs and basic theory of feedback amplifiers"--;Note continued: 12.5.6. Bias-Offset Cross-Coupled Differential Pairs -- 12.6. Bipolar Transconductors -- 12.6.1. Gain-Cell Transconductors -- 12.6.2. Transconductors Using Multiple Differential Pairs -- 12.7. BiCMOS Transconductors -- 12.7.1. Tunable MOS in Triode -- 12.7.2. Fixed-Resistor Transconductor with a Translinear Multiplier -- 12.7.3. Fixed Active MOS Transconductor with a Translinear Multiplier -- 12.8. Active RC and MOSFET-C Filters -- 12.8.1. Active RC Filters -- 12.8.2. MOSFET-C Two-Transistor Integrators -- 12.8.3. Four-Transistor Integrators -- 12.8.4.R-MOSFET-C Filters -- 12.9. Tuning Circuitry -- 12.9.1. Tuning Overview -- 12.9.2. Constant Transconductance -- 12.9.3. Frequency Tuning -- 12.9.4.Q-Factor Tuning -- 12.9.5. Tuning Methods Based on Adaptive Filtering -- 12.10. Introduction to Complex Filters -- 12.10.1.Complex Signal Processing -- 12.10.2.Complex Operations -- 12.10.3.Complex Filters -- 12.10.4. Frequency-Translated Analog Filters -- 12.11. Key Points -- 12.12. References -- 12.13. Problems -- ch. 13 Discrete-Time Signals -- 13.1. Overview of Some Signal Spectra -- 13.2. Laplace Transforms of Discrete-Time Signals -- 13.2.1. Spectra of Discrete-Time Signals -- 13.3.z-Transform -- 13.4. Downsampling and Upsampling -- 13.5. Discrete-Time Filters -- 13.5.1. Frequency Response of Discrete-Time Filters -- 13.5.2. Stability of Discrete-Time Filters -- 13.5.3. IIR and FIR Filters -- 13.5.4. Bilinear Transform -- 13.6. Sample-and-Hold Response -- 13.7. Key Points -- 13.8. References -- 13.9. Problems -- ch. 14 Switched-Capacitor Circuits -- 14.1. Basic Building Blocks -- 14.1.1. Opamps -- 14.1.2. Capacitors -- 14.1.3. Switches -- 14.1.4. Nonoverlapping Clocks -- 14.2. Basic Operation and Analysis -- 14.2.1. Resistor Equivalence of a Switched Capacitor -- 14.2.2. Parasitic-Sensitive Integrator -- 14.2.3. Parasitic-Insensitive Integrators -- 14.2.4. Signal-Flow-Graph Analysis -- 14.3. Noise in Switched-Capacitor Circuits -- 14.4. First-Order Filters -- 14.4.1. Switch Sharing -- 14.4.2. Fully Differential Filters -- 14.5. Biquad Filters -- 14.5.1. Low-Q Biquad Filter -- 14.5.2. High-Q Biquad Filter -- 14.6. Charge Injection -- 14.7. Switched-Capacitor Gain Circuits -- 14.7.1. Parallel Resistor-Capacitor Circuit -- 14.7.2. Resettable Gain Circuit -- 14.7.3. Capacitive-Reset Gain Circuit -- 14.8. Correlated Double-Sampling Techniques -- 14.9. Other Switched-Capacitor Circuits -- 14.9.1. Amplitude Modulator -- 14.9.2. Full-Wave Rectifier -- 14.9.3. Peak Detectors -- 14.9.4. Voltage-Controlled Oscillator -- 14.9.5. Sinusoidal Oscillator -- 14.10. Key Points -- 14.11. References -- 14.12. Problems -- ch. 15 Data Converter Fundamentals -- 15.1. Ideal D/A Converter -- 15.2. Ideal A/D Converter -- 15.3. Quantization Noise -- 15.3.1. Deterministic Approach -- 15.3.2. Stochastic Approach -- 15.4. Signed Codes -- 15.5. Performance Limitations -- 15.5.1. Resolution -- 15.5.2. Offset and Gain Error -- 15.5.3. Accuracy and Linearity -- 15.6. Key Points -- 15.7. References -- 15.8. Problems -- ch. 16 Nyquist-Rate D/A Converters -- 16.1. Decoder-Based Converters -- 16.1.1. Resistor String Converters -- 16.1.2. Folded Resistor-String Converters -- 16.1.3. Multiple Resistor-String Converters -- 16.1.4. Signed Outputs -- 16.2. Binary-Scaled Converters -- 16.2.1. Binary-Weighted Resistor Converters -- 16.2.2. Reduced-Resistance-Ratio Ladders -- 16.2.3.R-2R-Based Converters -- 16.2.4. Charge-Redistribution Switched-Capacitor Converters -- 16.2.5. Current-Mode Converters -- 16.2.6. Glitches -- 16.3. Thermometer-Code Converters -- 16.3.1. Thermometer-Code Current-Mode D/A Converters -- 16.3.2. Single-Supply Positive-Output Converters -- 16.3.3. Dynamically Matched Current Sources -- 16.4. Hybrid Converters -- 16.4.1. Resistor-Capacitor Hybrid Converters -- 16.4.2. Segmented Converters -- 16.5. Key Points -- 16.6. References -- 16.7. Problems -- ch. 17 Nyquist-Rate A/D Converters -- 17.1. Integrating Converters -- 17.2. Successive-Approximation Converters -- 17.2.1. DAC-Based Successive Approximation -- 17.2.2. Charge-Redistribution A/D -- 17.2.3. Resistor-Capacitor Hybrid -- 17.2.4. Speed Estimate for Charge-Redistribution Converters -- 17.2.5. Error Correction in Successive-Approximation Converters -- 17.2.6. Multi-Bit Successive-Approximation -- 17.3. Algorithmic (or Cyclic) A/D Converter -- 17.3.1. Ratio-Independent Algorithmic Converter -- 17.4. Pipelined A/D Converters -- 17.4.1. One-Bit-Per-Stage Pipelined Converter -- 17.4.2.1.5 Bit Per Stage Pipelined Converter -- 17.4.3. Pipelined Converter Circuits -- 17.4.4. Generalized k-Bit-Per-Stage Pipelined Converters -- 17.5. Flash Converters -- 17.5.1. Issues in Designing Flash A/D Converters -- 17.6. Two-Step A/D Converters -- 17.6.1. Two-Step Converter with Digital Error Correction -- 17.7. Interpolating A/D Converters -- 17.8. Folding A/D Converters -- 17.9. Time-Interleaved A/D Converters -- 17.10. Key Points -- 17.11. References -- 17.12. Problems -- ch. 18 Oversampling Converters -- 18.1. Oversampling without Noise Shaping -- 18.1.1. Quantization Noise Modelling -- 18.1.2. White Noise Assumption -- 18.1.3. Oversampling Advantage -- 18.1.4. The Advantage of 1-Bit D/A Converters -- 18.2. Oversampling with Noise Shaping -- 18.2.1. Noise-Shaped Delta-Sigma Modulator -- 18.2.2. First-Order Noise Shaping -- 18.2.3. Switched-Capacitor Realization of a First-Order A/D Converter -- 18.2.4. Second-Order Noise Shaping -- 18.2.5. Noise Transfer-Function Curves -- 18.2.6. Quantization Noise Power of 1-Bit Modulators -- 18.2.7. Error-Feedback Structure -- 18.3. System Architectures -- 18.3.1. System Architecture of Delta-Sigma A/D Converters -- 18.3.2. System Architecture of Delta-Sigma D/A Converters -- 18.4. Digital Decimation Filters -- 18.4.1. Multi-Stage -- 18.4.2. Single Stage -- 18.5. Higher-Order Modulators -- 18.5.1. Interpolative Architecture -- 18.5.2. Multi-Stage Noise Shaping (MASH) Architecture -- 18.6. Bandpass Oversampling Converters -- 18.7. Practical Considerations -- 18.7.1. Stability -- 18.7.2. Linearity of Two-Level Converters -- 18.7.3. Idle Tones -- 18.7.4. Dithering -- 18.7.5. Opamp Gain -- 18.8. Multi-Bit Oversampling Converters -- 18.8.1. Dynamic Element Matching -- 18.8.2. Dynamically Matched Current Source D/S Converters -- 18.8.3. Digital Calibration A/D Converter -- 18.8.4.A/D with Both Multi-Bit and Single-Bit Feedback -- 18.9. Third-Order A/D Design Example -- 18.10. Key Points -- 18.11. References -- 18.12. Problems -- ch. 19 Phase-Locked Loops -- 19.1. Basic Phase-Locked Loop Architecture -- 19.1.1. Voltage Controlled Oscillator -- 19.1.2. Divider -- 19.1.3. Phase Detector -- 19.1.4. Loop Filer -- 19.1.5. The PLL in Lock -- 19.2. Linearized Small-Signal Analysis -- 19.2.1. Second-Order PLL Model -- 19.2.2. Limitations of the Second-Order Small-Signal Model -- 19.2.3. PLL Design Example -- 19.3. Jitter and Phase Noise -- 19.3.1. Period Jitter -- 19.3.2.P-Cycle Jitter -- 19.3.3. Adjacent Period Jitter -- 19.3.4. Other Spectral Representations of Jitter -- 19.3.5. Probability Density Function of Jitter -- 19.4. Electronic Oscillators -- 19.4.1. Ring Oscillators -- 19.4.2. LC Oscillators -- 19.4.3. Phase Noise of Oscillators -- 19.5. Jitter and Phase Noise in PLLS -- 19.5.1. Input Phase Noise and Divider Phase Noise -- 19.5.2. VCO Phase Noise -- 19.5.3. Loop Filter Noise -- 19.6. Key Points -- 19.7. References -- 19.8. Problems.