Ebook: 5-Level Paging and 5-Level EPT White Paper
Author: coll.
- Genre: Technique // Electronics: Microprocessor Technology
- Series: Document Number: 335252-001
- Year: 2016
- Publisher: Intel Corporation
- Edition: Revision 1.0
- Language: English
- pdf
This document describes planned extensions to the Intel 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware.
Retrieved from https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf on 2017 May 09.
Retrieved from https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf on 2017 May 09.
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