Ebook: Abstract State Machines, B and Z: First International Conference, ABZ 2008, London, UK, September 16-18, 2008. Proceedings

This book constitutes the refereed proceedings of the First International Conference of Abstract State Machines, B and Z, ABZ 2008, held in London, UK, in September 2008. The conference simultaneously incorporated the 15th International ASM Workshop, the 17th International Conference of Z Users and the 8th International Conference on the B Method.

The 44 revised full papers presented together with 4 invited contributions were carefully reviewed and selected from numerous submissions. The conference fosters the cross-fertilization of three rigorous methods for the design and analysis of hardware and software systems - both in academia and industry - namely Abstract State Machines, B, and Z. Covering a wide range of research spanning from theoretical and methodological foundations to tool support and practical applications, the contributions are organized in topical sections on abstract state machines, B papers, Z papers, ABZ short papers, and the papers of the Verified Software Repository Network (VSR-net) workshop.

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Abstract. Complementary to the systems and software focus of the conference,this presentation will be about chips and the progress that has been made intheir functional verification. Common ground will be high-level, still cycleaccurate,state-based models of hardware functionalities called Abstract RT. RTstands for register transfer descriptions of hardware such as VHDL or Verilog.An Abstract RT model is a formal specification which permits an automatedformal comparison with its implementation, thus detecting any functionaldiscrepancy between code and formal specification.The first part of the presentation will sketch the big picture: Moore‘s Law stillholds and permits building huge chips comprising up to hundreds of millions ofgates. Under the constraints of shrinking budgets and development times, theseso-called systems-on-chip (SoC) can no longer be developed from scratch butmust largely be assembled from pre-designed, pre-verified design componentssuch as processors, controllers, a plethora of peripherals and large amounts ofmemories. Therefore, getting a SoC right depends to a large extent on the qualityof these design components – IP for short. At stake are critical errors making itinto silicon. These may cost millions of Euros due to delayed market entry,additional engineering and re-production efforts. Hence, the lion’s share oftoday’s verification efforts goes into the functional verification of such IP.