Ebook: Low Power Design Essentials

Low Power Design Essentials is the first book at the graduate level to address the design of low power digital integrated circuits in an orderly and logical fashion. As such, this book will be of interest to students as well as professionals. In addition to taking an educational approach towards low-power design, the book also presents an integrated methodology to address power at all layers of the design hierarchy. Finally, the text also explains the main roadblocks as well as the physical limits in further energy scaling.
This book is based on the extensive amount of teaching the author has carried out both at universities and companies worldwide. All chapters have been drawn up specifically for self-study. Different levels of understanding are included within each chapter. All chapters begin with elementary material and almost all contain advanced material.
A unique format is used for this book. Rather than the traditional approach of a lengthy continuous text interspersed with some figures, it uses the reverse approach of dominant graphics with accompanying suppplemental text. It is understood that a single figure does a lot more to convey a message than a page of text.
It is hoped that this innovative format provides a better structure for learning the essential topics in low power design.
About the Author
Jan Rabaey received his Ph.D degree in Applied Sciences from the Katholieke Universiteit Leuven, Belgium. From 1983-1985, he was connected to the UC Berkeley as a Visiting Research Engineer. From 1985-1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the FCRP-sponsored GigaScale Systems Research Center (GSRC). He is an IEEE Fellow.

The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction.

Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles.  The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions.

Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions.  Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.